library verilog;
use verilog.vl_types.all;
entity Left_Right_Swap is
    port(
        Left_Right_Swap_Input_Left: in     vl_logic_vector(32 downto 1);
        Left_Right_Swap_Input_Right: in     vl_logic_vector(32 downto 1);
        Left_Right_Swap_Select: in     vl_logic;
        Left_Right_Swap_Output: out    vl_logic_vector(64 downto 1);
        Left_Right_Swap_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end Left_Right_Swap;
